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Power Integrity Effects of High Density Interconnect (HDI)

Mentor Graphics

High Density Interconnect (HDI) is being used more often to meet the growing need for more complex designs in smaller form factors. Beyond some of the more obvious electrical effects of using smaller vias, there is also an impact to the power integrity of a board using HDI. This includes different effects of mounted inductances of decoupling capacitors, changes in plane performance due to reduction in perforation from chip pinouts, and the inherent plane-capacitance changes from using dielectrics of various thicknesses. This paper will examine and quantify these effects, using numerous design examples, including a large conventional through-hole design board that was reduced using HDI.

Tags : power integrity effects, mentor graphics, high density interconnect, hdi, chip pinouts, perforation, multilayer or build-up multilayer, bum, sequential build-up technologies, sbu, buried via holes, bvhs, dielectric materials, photosensitive, laser drilling, plasma drilling, microvia, plated through-holes, pths, power distribution network


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Published:  Apr 03, 2009
Length:  16
Type:  White Paper